standard cell design meaning in Chinese

标准单元设计

The focus of our research in the low - power design of viterbi decoders is reduction of dynamic power dissipation at logic level in the standard cell design environment
从这里发掘功耗的潜力是很大的,主要通过优化算法、优化逻辑结构来实现。
The serializer and deserializer moduls in the ftlvds chip are designed by the way of standard cell design approach . the paper emphatically discusses the tradeoff and the implementation of several clock synchronization modes and circuit structures , and makes a lot of verilog simulation and verification on the circuits designed
串并模块串行化器和解串行器采用标准单元的方法设计，论文讨论了对几种时钟同步模式以及串并转换电路结构的权衡和实现，并对所设计的电路结构进行了verilog模拟验证。